1. Field of the Invention
The present invention is generally in the field of semiconductor device fabrication. More particularly, the invention is in the field of semiconductor transistor fabrication.
2. Background Art
Integrated analog circuit designs often require multiple types of bipolar transistors that operate at different voltages to optimize different circuit blocks on a single semiconductor die. As a result, integrated circuit (IC) manufacturers have developed processes that allow high speed transistors with a relatively low breakdown voltage to be manufactured on the same semiconductor die as lower speed transistors with a high breakdown voltage. As a result of continuing advances in bipolar transistor technology, high speed transistors have been fabricated with a cutoff frequency (FT) of 200.0 megahertz (MHz) or greater. To fabricate these state of the art high speed bipolar transistors, a very thin epitaxial collector layer, which is formed over a highly doped, buried subcollector, is required to reduce collector transit time and collector resistance. However, the thickness of the epitaxial collector layer sets an upper limit on the collector-to-emitter breakdown voltage (BVCEO) of high voltage bipolar transistors that are to be fabricated on the same semiconductor substrate as the high speed bipolar transistors.
In a conventional bipolar fabrication process, for example, a high voltage transistor fabricated on the same semiconductor substrate with a high speed bipolar transistor having an FT of approximately 200.0 MHz or greater is generally limited to a BVCEO of between 3.0 volts and 4.0 volts. Although high voltage bipolar transistors having a BVCEO greater than 5.0 volts and high speed bipolar transistors having an FT of 200.0 MHz or greater can be integrated on the same die by growing separate epitaxial collector layers with different thicknesses, this conventional approach significantly increases manufacturing cost. Thus, a novel process for integrating high speed bipolar transistors having an FT of 200.0 MHz or greater with high voltage bipolar transistors having a BVCEO greater than 5.0 volts on a semiconductor substrate at a low manufacturing cost is highly desirable.